Design of A Low Power Low Voltage CMOS Opamp

摘要

In this paper a CMOS operational amplifier is presented which operates at 2Vpower supply and 1microA input bias current at 0.8 micron technology using nonconventional mode of operation of MOS transistors and whose input is dependedon bias current. The unique behaviour of the MOS transistors in subthresholdregion not only allows a designer to work at low input bias current but also atlow voltage. While operating the device at weak inversion results low powerdissipation but dynamic range is degraded. Optimum balance between powerdissipation and dynamic range results when the MOS transistors are operated atmoderate inversion. Power is again minimised by the application of inputdependant bias current using feedback loops in the input transistors of thedifferential pair with two current substractors. In comparison with thereported low power low voltage opamps at 0.8 micron technology, this opamp hasvery low standby power consumption with a high driving capability and operatesat low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is morethan other low power low voltage opamps reported at 0.8 um technology [1,2].Vittoz at al [3] reported that slew rate can be improved by adaptive biasingtechnique and power dissipation can be reduced by operating the device in weakinversion. Though lower power dissipation is achieved the area required by thecircuit is very large and speed is too small. So, operating the device inmoderate inversion is a good solution. Also operating the device insubthreshold region not only allows lower power dissipation but also a lowervoltage operation is achieved.